Track 1 Early Morning
Systematic Design of Bandgap Reference Circuit with Emphasis on Self-bias Loop Dynamics

Abstract

Sub-1V bandgap designs have recently become prominent candidates with the scaling of supply voltages and technology. The tutorial will brief the latest advances in the bandgap world with architectural descriptions and truly digital reverse bandgap design. Designing operational amplifiers for sub-1V bandgaps has become challenging for three primary reasons: the virtual node of the op-amps experiences a large swing, there is lower headroom for devices, and the bias current varies with temperature. Operational amplifier offset, particularly in bandgap designs, is critical as it gets amplified by the PTAT gain to the bandgap output. There are three primary types of offset: systematic offset, random offset, and random systematic offset. The only known solution for reducing systematic offset from the literature is self-bias, which replicates the bandgap current into the op-amp. However, the loop dynamics of self-bias, such as whether it operates as a positive or negative feedback loop, are seldom discussed in the literature. This tutorial will emphasize the impact of self-bias concerning DC gain and the negative feedback loop. The loop dynamics of self-bias are intriguing, as the feedback sign changes from negative to positive with frequency. This tutorial will present a detailed qualitative and quantitative analysis of the self-bias loop, providing design guidelines for implementing self-bias. The tutorial will brief you about the solution to random offset by chopping and describe the systematic analysis of the chopping technique specific to the bandgap world. Finally, the tutorial will conclude with the design of startup circuits. Known startup issues arise when the diodes carry extremely low currents, but there are also startup issues related to the maximum operational amplifier current introduced by the self-bias loop.

Speakers

Rajasekhar Nagulapalli
Analog Devices

Rajasekhar Nagulapalli received the B.Tech. degree in electrical engineering from Acharya Nagarjuna University, Guntur, India, in 2005, and the M.Tech. degree in microelectronics from the Indian Institute of Science, Bengaluru, India, in 2008 and PhD from Oxford Brookes, UK. From 2008 to 2011, he worked as PLL designer in Rambus, India After that he moved to IHP Germany to work on integrated optical chips.

In 2013 he joined Inphi-Uk as a principal engineer and led a 100Gb/s PAM-4 transceiver project and successfully deployed more 100 million ports in data centres across the world. Since 2021, he has been working in Analog devices (ADI) and leading the automotive SERDES development. He has 16 approved US patents and 10 are still pending. He is the author of > 50 IEEE papers with >1000 citations.

Rakesh Kumar Palani
Assistant Professor
IIT Delhi India

Rakesh K. Palani is currently working as an assistant professor in IIT-Delhi-India. He received his B. Tech. in electrical engineering from the National Institute of Technology, Kurukshetra, India in 2007 and his Ph. D. in electrical engineering from the University of Minnesota, Twin Cities in 2015. For his Ph.D., he worked on the design of PVT-tolerant inverter-based circuits for baseband analog applications. His research interest includes the design of low-power filters, ADCs, and amplifiers. In 2011, he was with Broadcom Corporation, Minneapolis, where he worked on the design of word line drivers for SRAM. In 2014, he was at Qualcomm, San Diego, where he worked on flicker noise reduction techniques in discrete time delta sigma modulators.